This invention relates to integrated circuit devices, and more particularly to a technique for protecting such devices against electrostatic discharge (ESD) damage.
As the number of power and/or ground buses within a device increases, achieving effective ESD protection of that device becomes more difficult. Conventional solutions for handling ESD between multiple power and/or ground buses often involve clamping an ESD protection circuit between each combination of power and ground buses. Such exhaustive cross-clamping soon becomes difficult, if not impractical, as the number of power and/or ground buses increases. Similarly, for the input/output (I/O) circuitry, applying conventional ESD protection techniques such as using large I/O transistors and/or providing complex ESD protection circuits for each I/O pad may become unwieldy as the number of power and/or ground buses increases.
The present invention relates to an improved technique for providing ESD protection for integrated circuit devices with multiple power and/or ground buses. The technique involves clamping each power bus, ground bus, and I/O pad within a device to a respective one of the ground buses. In accordance with the principles of the present invention, this arrangement provides a discharge path between any power bus, ground bus, and I/O pad during an ESD event without resorting to exhaustive cross-clamping. Moreover, this technique simplifies the I/O protection circuitry, thereby saving chip area and decreasing I/O capacitance.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the invention.